Peripheral component interconnect such as PCI Express (PCIe) is a high performance, generic and scalable system interconnect bus for a wide variety of applications ranging from personal computers to embedded applications. PCIe implements serial, full duplex, multi-lane, point-to-point interconnect, packet-based, and switch based technology. Current versions of PCIe buses allow for a transfer rate of 2.5 Gbps per lane, with a total of 32 lanes.
As illustrated in FIG. 1, the PCIe is a layered protocol bus, consisting of a transaction layer 110, a data link layer 120, and a physical layer 130. The PCIe implements split transactions, i.e., transactions with request and response separated by time, allowing the link to carry other traffic while the target device gathers data for the response. With this aim, the primary function of the transaction layer 110 is to assemble and disassemble transaction layer packets (TLPs). TLPs are used to carry transactions, where each TLP has a unique identifier that enables a response directed at the originator. The data link layer 120 acts as an intermediate between the transaction layer 110 and the physical layer 130 and provides a reliable mechanism for exchanging TLPs. The data link layer 120 implements error checking (known as “link cyclic redundancy check (LCRC)”) and retransmission mechanisms. LCRC and sequencing are applied on received TLPs and if an error is detected, a data link retry is activated. The physical layer 130 consists of a logical sub-layer 132 and an electrical sub-layer 134. The logical sub-layer 132 is a transmitter and receiver pair implementing symbol mapping, serialization and de-serialization of data. At the electrical sub-layer 134, each lane utilizes two unidirectional low-voltage differential signaling (LVDS) pairs at 2.5 Gbit/s or 5 Gbit/s to transmit and receive symbols from the logical sub-layer 132.
In the current technology, peripheral components are physically coupled to the PCIe. Recently, an effort is being made to wirelessly connect the peripheral devices to a computer. For example, a wireless USB technology for USB and Wi-Fi is a standard for Ethernet connection. However, each such wireless interconnect solution can support the connectivity of only a limited set of peripheral devices.
More advanced solutions propose a wireless peripheral interconnect bus, thereby allowing de-coupling of all peripheral devices connected to a computer. In order to enable efficient wireless transmissions peripheral interconnect bus solutions must guarantee low latency and reliable transmissions of data between the peripheral components of a wireless peripheral interconnect bus.